With the design loaded and constraints applied, you can compile the logic. Standard synthesis uses wireload models, while Topographical Mode uses physical data from a floorplan to calculate accurate interconnect delays. Running Basic Compile
Strengths
Before passing your design to the physical layout phase, analyze the output text files generated during Step 5. Timing Report Analysis synopsys design compiler tutorial 2021
The DC 2021 flow consists of four compulsory phases:
Design Compiler automatically reads configuration files upon initialization. Create a file named .synopsys_dc.setup in your project root or home directory to define system variables. Key Library Variables With the design loaded and constraints applied, you
Input and output ports operate relative to external system components. You must tell DC how much time is consumed outside your module.
DC 2021 can read a preliminary floorplan to estimate routing congestion. Timing Report Analysis The DC 2021 flow consists
Look at the line at the bottom of a generated timing path report:
# ---------------------------------------- # Synopsys DC 2021 Tutorial Script # ----------------------------------------
# Define path directories set project_path "/home/user/project/synthesis" set lib_path "/opt/foundry/tsmc/65nm/libs" # Configure search path set search_path [list . $project_path/rtl $lib_path/db $search_path] # Configure libraries set target_library [list tsmc65nm_ss_0v9_125c.db] set link_library [list * tsmc65nm_ss_0v9_125c.db sram_2kx32_ss.db] set symbol_library [list tsmc65nm.sdb] # Define work directory mapping define_design_lib WORK -path ./WORK echo "--- Synthesis Environment Setup Complete ---" Use code with caution. 3. Reading and Analyzing the Design
set_power_options -leakage -dynamic set_max_leakage_power 0.1 mW compile_ultra -power_high_effort